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? semiconductor components industries, llc, 2013 february, 2013 ? rev. 1 1 publication order number: ncv8770/d ncv8770 ultra low i q 350 ma ldo regulator with reset the ncv8770 is 350 ma ldo regulator with integrated reset functions dedicated for microprocesso r applications. its robustness allows ncv8770 to be used in severe automotive environments. ultra low quiescent current as low as 21 a typical makes it suitable for applications permanently connected to battery requiring ultra low quiescent current with or without load. this feature is especially critical when modules remain in active mode when ignition is off. the ncv8770 contains protection functions as current limit, thermal shutdown and reverse output current protection. features ? output voltage options: 5 v ? output voltage accuracy: 1.5% (t j = 25 c to 125 c) ? output current up to 350 ma ? ultra low quiescent current: typ 21 a (max 28 a) ? very wide range of c out and esr values for stability ? microprocessor compatible control functions: ? reset with adjustable power ? on delay ? wide input voltage operation range: up to 40 v ? protection features ? current limitation ? thermal shutdown ? these are pb ? free devices typical applications ? body control module ? instruments and clusters ? occupant protection and comfort ? powertrain ncv8770 gnd figure 1. typical application schematic v in v out reset microprocessor c out 1 f c in 0.1 f v bat v out v dd ro dt http://onsemi.com marking diagrams see detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet. ordering information y = timing and reset threshold option xx = voltage option a = assembly location wl, l = wafer lot y = year ww = work week g or = pb ? free package d 2 pak ? 5 d5s suffix case 936a nc v8770yxx awlywwg 770yxxg alyww dpak ? 5 dt suffix case 175aa
ncv8770 http://onsemi.com 2 driver with current limit gnd ro thermal shutdown timer reference erorr amplifier reset comparator timing circuit reset driver figure 2. simplified block diagram v in v out * pull ? down resistor (typ 150 k ) active only in reset state dt * pin connections 1 figure 3. pin connections d 2 pak ? 5 pin 1. v in 2. ro tab, 3. gnd 4. dt 5. v out dpak ? 5 pin 1. v in 2. ro tab, 3. gnd 4. dt 5. v out 1 pin function description pin no. dpak ? 5 d2pak ? 5 pin name description 1 v in positive power supply input. connect 0.1 f capacitor to ground. 2 ro reset output. 30 k internal pull ? up resistor connected to v out . ro goes low when v out drops by more than 7% (typ) from its nominal value (for ncv8770y devices with y = 1,2,3,...) or more than 10% (typ) from its nominal value (for ncv8770y devices with y = a, b, c,...). 3, tab gnd power supply ground. 4 dt reset delay time select. short to gnd or connected to v out to select time. 5 v out regulated output voltage. connect 1 f capacitor with esr < 100 to ground. ? nc not connected ? gnd exposed pad is connected to ground.
ncv8770 http://onsemi.com 3 absolute maximum ratings rating symbol min max unit input voltage (note 1) dc transient, t < 100 ms v in ? 0.3 ? 40 45 v input current i in ? 5 ? ma output voltage (note 2) v out ? 0.3 5.5 v output current i out ? 3 current limited ma dt (reset delay time select) voltage v dt ? 0.3 5.5 v dt (reset delay time select) current i dt ? 1 1 ma reset output voltage v ro ? 0.3 5.5 v reset output current i ro ? 3 3 ma junction temperature t j ? 40 150 c storage temperature t stg ? 55 150 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. refer to electrical characteristics and application information for safe operating area. 2. 5.5 v or (v in + 0.3 v) (whichever is lower). esd capability (note 3) rating symbol min max unit esd capability, human body model esd hbm ? 2 2 kv esd capability, machine model esd mm ? 200 200 v esd capability, charged device model esd cdm ? 1 1 kv 3. this device series incorporates esd protection and is tested by the following methods: esd human body model tested per aec ? q100 ? 002 (js ? 001 ? 2010) esd machine model tested per aec ? q100 ? 003 (eia/jesd22 ? a115) esd charge device model tested per aec ? q100 ? 011 (eia/jesd22 ? c101) lead soldering temperature and msl (note 4) rating symbol min max unit moisture sensitivity level dpak ? 5 d2pak ? 5 msl 1 1 ? lead temperature soldering reflow (smd styles only), pb ? free versions t sld ? 265 peak c 4. for more information, please refer to our soldering and mounting techniques reference manual, solderrm/d. thermal characteristics (note 5) rating symbol value unit thermal characteristics, dpak ? 5 thermal resistance, junction ? to ? air (note 6) thermal reference, junction ? to ? case (note 6) r ja r jc 56 8.4 c/w thermal characteristics, d2pak ? 5 thermal resistance, junction ? to ? air (note 6) thermal reference, junction ? to ? case (note 6) r ja r jc 53 8.4 c/w 5. refer to electrical characteristics and application information for safe operating area. 6. values based on copper area of 645 mm 2 (or 1 in 2 ) of 1 oz copper thickness and fr4 pcb substrate. recommended operating range (note 7) rating symbol min max unit input voltage (note 8) v in 5.5 40 v junction temperature t j ? 40 150 c 7. refer to electrical characteristics and application information for safe operating area. 8. minimum v in = 5.5 v or (v out + v do ), whichever is higher.
ncv8770 http://onsemi.com 4 electrical characteristics v in = 13.2 v, c in = 0.1 f, c out = 1 f, for typical values t j = 25 c, for min/max values t j = ? 40 c to 150 c; unless otherwise noted. (notes 9 and 10) parameter test conditions symbol min typ max unit regulator output output voltage (accuracy %) t j = 25 c to 125 c v in = 5.575 v to 16 v, i out = 0.1 ma to 200 ma v out 4.925 ( ? 1.5 %) 5.0 5.075 (+1.5%) v output voltage (accuracy %) v in = 5.6 v to 40 v, i out = 0.1 ma to 200 ma v in = 5.975 v to 16 v, i out = 0.1 ma to 350 ma v out 4.9 4.9 ( ? 2 %) 5.0 5.0 5.1 5.1 (+2%) v output voltage (accuracy %) t j = ? 40 c to 125 c v in = 5.975 v to 28 v, i out = 0 ma to 350 ma v out 4.9 ( ? 2 %) 5.0 5.1 (+2%) v line regulation v in = 6 v to 28 v, i out = 5 ma reg line ? 20 0 20 mv load regulation i out = 0.1 ma to 350 ma reg load ? 35 0 35 mv dropout voltage (note 11) i out = 200 ma i out = 350 ma v do ? ? 250 440 500 875 mv quiescent current quiescent current (i q = i in ? i out ) i out = 0.1 ma, t j = 25 c i out = 0.1 ma to 350 ma, t j 125 c i q ? ? 21 ? 27 28 a current limit protection current limit v out = 0.96 x v out_nom i lim 400 ? 1100 ma short circuit current limit v out = 0 v i sc 400 ? 1100 ma psrr power supply ripple rejection (note 12) f = 100 hz, 0.5 v pp psrr ? 54 ? db dt (reset delay time select) dt threshold voltage logic low logic high v th(dt) ? 2.0 ? ? 0.8 ? v dt input current v dt = 5 v i dt ? ? 1.0 a 9. refer to absolute maximum ratings and application information for safe operating area. 10. performance guaranteed over the indicated operating temperature range by design and/or characterization tested at t a t j . low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible. 11. measured when output voltage falls 100 mv below the regulated voltage at v in = 13.2 v. 12. values based on design and/or characterization. 13. see application information section for reset thresholds and reset delay time options
ncv8770 http://onsemi.com 5 electrical characteristics v in = 13.2 v, c in = 0.1 f, c out = 1 f, for typical values t j = 25 c, for min/max values t j = ? 40 c to 150 c; unless otherwise noted. (notes 9 and 10) parameter unit max typ min symbol test conditions reset output ro output voltage reset threshold (note 13) (ncv8770y) where y = 1,2,3,... 5.0 v (ncv8770y) where y = a,b,c,... 5.0 v v out decreasing, v in > 5.5 v v rt 90 87 93 90 96 93 %v out reset hysteresis v rh ? 2.0 ? %v out maximum reset sink current v out = 4.5 v, v ro = 0.25 v i romax 1.75 ? ? ma reset output low voltage v out > 1 v, i ro < 200 a v rol ? 0.15 0.25 v reset output high voltage v roh 4.5 ? ? v integrated reset pull ? up resistor r ro 15 30 50 k reset delay time (note 13) min available time, dt connected to gnd max available time, dt connected to v out t rd 3.2 102.4 ? 20% 4.0 128 4.8 153.6 +20% ms reset reaction time (see figure 21) t rr 16 25 38 s thermal shutdown thermal shutdown temperature (note 12) t sd 150 175 195 c thermal shutdown hysteresis (note 12) t sh ? 25 ? c 9. refer to absolute maximum ratings and application information for safe operating area. 10. performance guaranteed over the indicated operating temperature range by design and/or characterization tested at t a t j . low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible. 11. measured when output voltage falls 100 mv below the regulated voltage at v in = 13.2 v. 12. values based on design and/or characterization. 13. see application information section for reset thresholds and reset delay time options
ncv8770 http://onsemi.com 6 typical characteristics figure 4. quiescent current vs. temperature 18 19 20 21 22 23 24 25 26 27 28 ? 40 ? 20 0 20 40 60 80 100 120 140 160 t j , junction temperature ( c) i q , quiescent current ( a) v in = 13.2 v i out = 100 a figure 5. quiescent current vs. input voltage 0 50 100 150 200 250 0 5 10 15 20 25 30 35 40 v in , input voltage (v) i q , quiescent current ( a) i out = 0 ma t j = 25 c figure 6. quiescent current vs. output current 18 19 20 21 22 23 24 25 26 27 28 0 50 100 150 200 250 300 350 i q , quiescent current ( a) i out , output current (ma) v in = 13.2 v t j = 25 c t j = ? 40 c t j = 150 c figure 7. output voltage vs. temperature 4.90 4.95 5.00 5.05 5.10 ? 40 ? 20 0 20 40 60 80 100 120 140 160 t j , junction temperature ( c) v out , output voltage (v) v in = 13.2 v i out = 100 a figure 8. output voltage vs. input voltage 0 1 2 3 4 5 6 012345678 v in , input voltage (v) v out , output voltage (v) t j = 150 c t j = ? 40 c t j = 25 c i out = 1 ma figure 9. dropout vs. output current 0 100 200 300 400 500 600 700 800 0 50 100 150 200 250 300 350 v do , dropout voltage (mv) i out , output current (ma) t j = 150 c t j = ? 40 c t j = 25 c
ncv8770 http://onsemi.com 7 typical characteristics figure 10. dropout vs. temperature 0 100 200 300 400 500 600 700 800 ? 40 ? 20 0 20 40 60 80 100 120 140 160 t j , junction temperature ( c) v do , dropout voltage (mv) figure 11. output current limit vs. input voltage 0 100 200 300 400 500 600 700 800 0 5 10 15 20 25 30 35 40 v in , input voltage (v) i lim , i sc , current limit (ma) t j = 25 c i out = 350 ma i out = 200 ma i sc @ v out = 0 v i lim @ v out = 4.8 v figure 12. output current limit vs. temperature 400 450 500 550 600 650 700 750 800 ? 40 ? 20 0 20 40 60 80 100 120 140 160 t j , junction temperature ( c) i lim , i sc , current limit (ma) v in = 13.2 v figure 13. c out esr stability region vs. output current i sc @ v out = 0 v i lim @ v out = 4.8 v 0.01 0.1 1 10 100 0 50 100 150 200 250 300 350 i out , output current (ma) esr, stability region ( ) stable region v in = 13.2 v t j = ? 40 c to 150 c c out = 1 f ? 100 f figure 14. line transients figure 15. load transients time (1 ms/div) 12.2 v 14.2 v 13 v v in (1 v/div) 5 v 5.16 v 4.95 v time (50 us/div) 0.1 ma 100 ma 5 v 4.77 v 5.16 v v out (100 mv/div) v out (100 mv/div) i out (50 ma/div) t j = 25 c i out = 1.0 ma c out = 10 f t rise/fall = 1 s (v in ) t j = 25 c v in = 13.2 v c out = 10 f t rise/fall = 1 s (i out )
ncv8770 http://onsemi.com 8 typical characteristics figure 16. power up/down response t j = 25 c v en = v in r out = 5 k v in (5 v/div) v out (5 v/div) time (100 ms/div) v ro (5 v/div) figure 17. psrr vs. frequency 0 10 20 30 40 50 60 70 80 90 100 10 100 1000 10000 100000 f, frequency (hz) psrr (db) t j = 25 c v in = 13.2 v 0.5 v pp c out = 1 f i out = 1.0 ma figure 18. noise vs. frequency 0 500 1000 1500 2000 2500 3000 3500 4000 5000 10 100 1000 10000 100000 noise density (nv/ hz ) f, frequency (hz) t j = 25 c v in = 13.2 v c out = 1 f i out = 350 ma figure 19. reset threshold vs. temperature 4.60 4.65 4.70 4.75 4.80 ? 40 ? 20 0 20 40 60 80 100 120 140 160 t j , junction temperature ( c) v rt , reset threshold (v) v in = 13.2 v figure 20. reset delay time vs. temperature 12 14 16 18 20 ? 40 ? 20 0 20 40 60 80 100 120 140 160 t j , junction temperature ( c) t rd , reset delay time (ms) v in = 13.2 v 4500 13 15 17 19
ncv8770 http://onsemi.com 9 t t t figure 21. reset function and timing diagram < t rr t rr t rd v in v out v rt v rt + v rh v ro v roh v rol definitions general all measurements are performed using short pulse low duty cycle techniques to maintain junction temperature as close as possible to ambient temperature. output voltage the output voltage parameter is defined for specific temperature, input voltage and output current values or specified over line, load and temperature ranges. line regulation the change in output voltage for a change in input voltage measured for specific output current over operating ambient temperature range. load regulation the change in output voltage for a change in output current measured for specific input voltage over operating ambient temperature range. dropout voltage the input to output differential at which the regulator output no longer maintains regulation against further reductions in input voltage. it is measured when the output drops 100 mv below its nominal value. the junction temperature, load current, and minimum input supply requirements affect the dropout level. quiescent current quiescent current (i q ) is the difference between the input current (measured through the ldo input pin) and the output load current. current limit and short circuit current limit current limit is value of output current by which output voltage drops below 96% of its nominal value. short circuit current limit is output current value measured with output of the regulator shorted to ground. psrr power supply rejection ratio is defined as ratio of output voltage and input voltage ripple. it is measured in decibels (db). line transient response typical output voltage overshoot and undershoot response when the input voltage is excited with a given slope. load transient response typical output voltage overshoot and undershoot response when the output current is excited with a given slope between low ? load and high ? load conditions. thermal protection internal thermal shutdown circuitry is provided to protect the integrated circuit in the event that the maximum junction temperature is exceeded. when activated at typically 175 c, the regulator turns off. this feature is provided to prevent failures from accidental overheating. maximum package power dissipation the power dissipation level is maximum allowed power dissipation for particular package or power dissipation at which the junction temperature reaches its maximum operating value, whichever is lower.
ncv8770 http://onsemi.com 10 applications information the ncv8770 regulator is self ? protected with internal thermal shutdown and internal current limit. typical characteristics are shown in figure 4 to figure 21. input decoupling (c in ) a ceramic or tantalum 0.1 f capacitor is recommended and should be connected close to the ncv8770 package. higher capacitance and lower esr will improve the overall line and load transient response. if extremely fast input voltage transients are expected then appropriate input filter must be used in order to decrease rising and/or falling edges below 50 v/ s for proper operation. the filter can be composed of several capacitors in parallel. output decoupling (c out ) the ncv8770 is a stable component and does not require a minimum equivalent series resistance (esr) for the output capacitor. stability region of esr vs output current is shown in figure 13. the minimum output decoupling value is 1 f and can be augmented to fulfill stringent load transient requirements. the regulator works with ceramic chip capacitors as well as tantalum devices. larger values improve noise rejection and load regulation transient response. reset operation a reset signal is provided on the reset output (ro) pin to provide feedback to the microprocessor of an out of regulation condition. the timing diagram of reset function is shown in figure 21. this is in the form of a logic signal on ro. output voltage conditions below the reset threshold cause ro to go low. the ro integrity is maintained down to v out = 1.0 v. for 5 v voltage option, the reset output (ro) circuitry includes internal pull ? up (30 k ) connected to the output (v out ) no external pull ? up is necessary. reset delay time select selection of the ncv8770y devices and the state of the dt pin determines the available reset delay times. the part is designed for use with dt tied to ground or v out , but may be controlled by any logic signal which provides a threshold between 0.8 v and 2 v. the default condition for an open dt pin is the slower reset time (dt = gnd condition). times are in pairs and are highlighted in the chart below. consult factory for availability. the delay time select (dt) pin is logic level controlled and provides reset delay time per the chart. note the dt pin is sampled only when ro is low, and changes to the dt pin when ro is high will not effect the reset delay time. reset delay and reset threshold options dt = gnd reset time dt = v out reset time reset threshold ncv87701 8 ms 128 ms 93% ncv87702 8 ms 32 ms 93% ncv87703 16 ms 64 ms 93% ncv87704 32 ms 128 ms 93% ncv87705 4 ms 8 ms 93% ncv87706 16 ms 128 ms 93% ncv8770a 8 ms 128 ms 90% ncv8770b 8 ms 32 ms 90% ncv8770c 16 ms 64 ms 90% ncv8770d 32 ms 128 ms 90% ncv8770e 4 ms 8 ms 90% ncv8770f 16 ms 128 ms 90% note: the timing values can be selected from the following list: 4, 8, 16, 32, 64, 128 ms. contact factory for options not included in ordering information table on following page. thermal considerations as power in the ncv8770 increases, it might become necessary to provide some thermal relief. the maximum power dissipation supported by the device is dependent upon board design and layout. mounting pad configuration on the pcb, the board material, and the ambient temperature affect the rate of junction temperature rise for the part. when the ncv8770 has good thermal conductivity through the pcb, the junction temperature will be relatively low with high power applications. the maximum dissipation the ncv8770 can handle is given by: p d ( max ) t j(max) t a r ja (eq. 1) since t j is not recommended to exceed 150 c, then the ncv8770 soldered on 645 mm 2 , 1 oz copper area, fr4 can dissipate up to 2.35 w (for d2pak ? 5) when the ambient temperature (t a ) is 25 c. see figure 22 for r ja versus pcb area. the power dissipated by the ncv8770 can be calculated from the following equations: p d v in i q @i out
i out v in v out (eq. 2) or v in(max) p d(max)
v out i out i out
i q (eq. 3) note: items containing i q can be neglected if i out >> i q .
ncv8770 http://onsemi.com 11 figure 22. thermal resistance vs. pcb copper area 40 50 60 70 80 90 100 0 100 200 300 400 500 600 700 copper heat spreader (mm 2 ) r ja , thermal resistance ( c/w) d 2 pak 1 oz d 2 pak 2 oz dpak 1 oz dpak 2 oz hints v in and gnd printed circuit board traces should be as wide as possible. when the impedance of these traces is high, there is a chance to pick up noise or cause the regulator to malfunction. place external components, especially the output capacitor, as close as possible to the ncv8770 and make traces as short as possible. ordering information device output voltage reset delay time (dt = gnd/v out ) reset threshold marking package shipping ? NCV87706DT50RKG 5.0 v 16/128 ms 93% 770650g dpak ? 5 (pb ? free) 2500 / tape & reel ncv87706ds50r4g 5.0 v 16/128 ms 93% nc v8770650 d2pak ? 5 (pb ? free) 800 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncv8770 http://onsemi.com 12 package dimensions dpak 5, center lead crop case 175aa issue a *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. d a k b r v s f l g 5 pl m 0.13 (0.005) t e c u j h ? t ? seating plane z dim min max min max millimeters inches a 0.235 0.245 5.97 6.22 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.020 0.028 0.51 0.71 e 0.018 0.023 0.46 0.58 f 0.024 0.032 0.61 0.81 g 0.180 bsc 4.56 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.102 0.114 2.60 2.89 l 0.045 bsc 1.14 bsc r 0.170 0.190 4.32 4.83 s 0.025 0.040 0.63 1.01 u 0.020 ??? 0.51 ??? v 0.035 0.050 0.89 1.27 z 0.155 0.170 3.93 4.32 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. r1 0.185 0.210 4.70 5.33 r1 1234 5 6.4 0.252 0.8 0.031 10.6 0.417 5.8 0.228 scale 4:1 mm inches 0.34 0.013 5.36 0.217 2.2 0.086 soldering footprint*
ncv8770 http://onsemi.com 13 package dimensions d 2 pak 5 case 936a ? 02 issue c 5 ref a 123 k b s h d g c e m l p n r v u terminal 6 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. tab contour optional within dimensions a and k. 4. dimensions u and v establish a minimum mounting surface for terminal 6. 5. dimensions a and b do not include mold flash or gate protrusions. mold flash and gate protrusions not to exceed 0.025 (0.635) maximum. dim a min max min max millimeters 0.386 0.403 9.804 10.236 inches b 0.356 0.368 9.042 9.347 c 0.170 0.180 4.318 4.572 d 0.026 0.036 0.660 0.914 e 0.045 0.055 1.143 1.397 g 0.067 bsc 1.702 bsc h 0.539 0.579 13.691 14.707 k 0.050 ref 1.270 ref l 0.000 0.010 0.000 0.254 m 0.088 0.102 2.235 2.591 n 0.018 0.026 0.457 0.660 p 0.058 0.078 1.473 1.981 r 5 ref s 0.116 ref 2.946 ref u 0.200 min 5.080 min v 0.250 min 6.350 min 45 m 0.010 (0.254) t ? t ? optional chamfer 8.38 0.33 1.016 0.04 16.02 0.63 10.66 0.42 3.05 0.12 1.702 0.067 scale 3:1 mm inches soldering footprint* *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ncv8770/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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